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Principal ASIC Engineer GPS
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Location: Anaheim
Job type: Permanent
Aircraft type:
Contact:
Sector: Flight Crew
Job Role:
-
Requisition ID
108440
USA-California-Anaheim
Description
Principal ASIC Engineer
We are a company of innovators, game changers, and entrepreneurs. As a prime contractor, we provide a broad range of communication, electronic and sensor systems used on military and commercial platforms across the globe. We embrace innovative and progressive ideas to advance our products for military and commercial customers. The Electronic Systems Segment (ESS) provides a broad range of aerospace systems, security and detection systems, and pilot training.
The L3 Interstate Electronics Corporation Division was founded in 1956 and for over 60 years IEC has played a key role in the most successful defense system of modern history. Headquartered in Anaheim, CA, IEC is a recognized industry leader in defense and security solutions, providing critical technology advancements in the areas of GPS/ Position Navigation and Timing, and Range and Test Solutions.
Job Summary:
Under limited supervision and with moderate latitude in assignment perform ASIC design work developing a GPS receiver System on a Chip (SoC). The job requires the ownership of signal processing subsystems of the ASIC including design and verification along with traceability to requirements. A knowledge of GPS signal processing ASIC/FPGA design and verification process from requirements specifications, ASIC design, ASIC verification testing, Requirements Review, Design Review, is a requirement. Knowledge of hardware emulation is a plus.
Values are an integral part of who we are. We seek candidates who share our values:
• Integrity
• Excellence
• Accountability
• Respect
Qualifications
Required Education/Experience :
* Masters of Science degree in Electrical Engineering or equivalent required.
* 10-15 years experience leading the development of large digital ASIC/SOCs.
* Applicants should have experience in the IC/ASIC development flow from concept through production release of silicon.
* Experience in defining and using advanced front-end design flows from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team.
* Experience in high-speed analog block integration (30GHz ADCs) into digital logic, high speed SERDES interfaces and multi-channel systems.
* Well-developed ability to analyze specifications at the architecture a micro-architecture level to identify design improvements.
* Experience with ASIC verification using random constraint coverage driven verification methodology like UVM, VMM, OVM or SPECMAN.
* Fluency with Verilog and System Verilog, experience with synthesis, formal verification, at STA flow setup.
* Experience in DSP block implementation highly desirable.
* Excellent program management and people management, communications, and project tracking skills required.
* Capable of working in a team environment along with the ability to work independently with minimal direction.
* Some weekends and evenings will be required.
Special Requirements: Applicants selected will be subject to a government security investigation and must meet and maintain eligibility requirements for access to DoD classified information.
SAVING LIVES AND MAKING THE WORLD A SAFER PLACE TO LIVE
L3 Technologies, Inc. is proud to be an Affirmative Action/Equal Opportunity Employer. L3 provides equal employment opportunity for all persons, in all facets of employment. L3 maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks. We encourage all qualified applicants to apply for any open position for which they feel they are qualified and all will receive consideration for employment without regard to race, color, religion, age, gender, sexual orientation, gender identity, national origin, citizenship status, marital status, genetic information, disability, protected veteran status or any other legally protected characteristic.
US Security Clearance Required
:
Secret
Schedule
:
Full-time
Shift
:
Day - 1st
Travel
:
Yes, 10 % of the Time
Organization
:
Division - Interstate Electronics-20000053
Job Level
:
Individual Contributor
Job Posting
:
Jun 4, 2019, 4:57:28 PM
Job
:
Engineering-Electrical
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